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Week - 1 |
Principles of a system-on-chip (SoC) design, SoC design flow, design reuse |
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Week - 2 |
HW/SW codesign, embedded systems and FPGA, hardware acceleration, interface design, IP core design |
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Week - 3 |
Zynq architecture, processing system, programmable logic, interfacing and signals, interconnection networks, memory, interrupts |
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Week - 4 |
System-on-chip development, HW/SW partitioning, profiling, software development tools |
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Week - 5 |
Midterm 1 |
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Week - 6 |
ARM AXI interfacing, architecture, transactions, IP core design methods, Custom IP core design through HDL |
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Week - 7 |
Simulation, memory mapped I/O, device drivers, interrupt handlers |
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Week - 8 |
High level synthesis (HLS), user interfaces, data types, interface specification and synthesis, algorithm synthesis |
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Week - 9 |
IP core design via HLS, Designing a SoC architectures for a data intensive application |
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Week - 10 |
IP reuse and integration |
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Week - 11 |
Operating systems on SoC, Linux kernel, memory management, process management |
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Week - 12 |
Linux booting, First-Stage Bootloader (FSBL), booting Zynq |
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Week - 13 |
Direct Memory Access (DMA), DMA transfer from DDR and OCM |
Eskisehir Technical University Info Package 
Turkish 
English