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Week - 1 |
VHDL Introduction |
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Week - 2 |
VHDL Design Styles |
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Week - 3 |
Concurrent Signal Assignment |
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Week - 4 |
VHDL Operators |
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Week - 5 |
Combinational Logic Circuits |
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Week - 6 |
EN: Sequential Signal Assignment |
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Week - 7 |
EN: Synchronous Sequential Circuit Design |
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Week - 8 |
EN: Finite State Machines |
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Week - 9 |
EN: Register Transfer Methodology |
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Week - 10 |
EN: Finite State Machines with Datapath |
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Week - 11 |
EN: Advanced Digital Circuit Design Examples |
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Week - 12 |
EN: Clock and Synchronization |