Akademik Dersler - İçerik

0 : Does not support 1 : Low-level support 2 : Mid-level support 3 : Top level support

Learning Outcomes	1	2	3	4	5	6	7	8	9	10	11
Will be able to explain the basic features of VHDL	1	2	1	2	2	1	1	1	0	0	0
Will be able to design and verify combinational circuits using VHDL	1	2	1	2	2	1	1	1	0	0	0
Will be able to implement and verify combinational circuits on FPGA	1	2	1	2	2	1	1	1	0	0	0
Will be able to design and verify synchronous sequential circuits using VHDL	1	2	1	2	2	1	1	1	0	0	0
Will be able to implement and verify synchronous sequential circuits on FPGA	1	2	1	2	2	1	1	1	0	0	0
Will be able to design and verify finite state machines using VHDL	-	-	-	-	-	-	-	-	-	-	-
Will be able to implement and verify finite state machines on FPGA	1	2	1	2	2	1	1	1	0	0	0