|
Week - 1 |
VHDL Introduction |
|
Week - 2 |
VHDL Design Styles |
|
Week - 3 |
Concurrent Signal Assignment |
|
Week - 4 |
VHDL Operators |
|
Week - 5 |
Combinational Logic Circuits |
|
Week - 6 |
Midterm |
|
Week - 7 |
Sequential Signal Assignment |
|
Week - 8 |
Synchronous Sequential Circuit Design |
|
Week - 9 |
Finite State Machines |
|
Week - 10 |
Register Transfer Methodology |
|
Week - 11 |
Midterm |
|
Week - 12 |
Finite State Machines with Datapath |
|
Week - 13 |
Advanced Digital Circuit Design Examples |
|
Week - 14 |
Clock and Synchronization |